UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11265

3.1i ChipScope Core Inserter - NGO with unconnected logic is created: "ERROR:MapLib:32 - LUT3 symbol"

Description

Keywords: ChipScope, inserter, MapLib

Urgency: Standard

General Description:
When I create an ILA core with a data width of 65 and a data depth of 4096, the following warnings appear in NGDBuild:

WARNING:NgdBuild:440 - FF primitive
'U_ila0/ila/i_dt0/1/storage/ila_ram_i/mux_if/1/fi/1/u_fde' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'U_ila0/ila/i_dt0/1/storage/ila_ram_i/mux_if/1/fi/2/u_fde' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'U_ila0/ila/i_dt0/1/storage/ila_ram_i/mux_if/1/fi/3/u_fde' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'U_ila0/ila/i_dt0/1/storage/ila_ram_i/mux_if/1/fi/4/u_fde' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'U_ila0/ila/i_dt0/1/storage/ila_ram_i/mux_if/1/fi/5/u_fde' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'U_ila0/ila/i_dt0/1/storage/ila_ram_i/mux_if/1/fi/6/u_fde' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'U_ila0/ila/i_dt0/1/storage/ila_ram_i/mux_if/1/fi/7/u_fde' has unconnected output pin
WARNING:NgdBuild:452 - logical net 'icon_control0<2>' has no driver
WARNING:NgdBuild:452 - logical net 'icon_control0<11>' has no driver
WARNING:NgdBuild:454 - logical net 'icon_control0<11>' has no load
WARNING:NgdBuild:452 - logical net 'icon_control0<12>' has no driver
WARNING:NgdBuild:454 - logical net 'icon_control0<12>' has no load
WARNING:NgdBuild:454 - logical net 'icon_control0<14>' has no load

The following error then occurs in MAP:

ERROR:MapLib:32 - LUT3 symbol
"U_icon/icon_1/u_icon_core/i_eq1to2/1/u_ila_data_tdo1/i1/1/u_lut" (output signal=U_icon/u_icon_core/tdo1_vec_2) has an equation that uses an input pin connected to a trimmed signal. Make sure that all the pins used in the equation for this LUT have signals that are not trimmed (see trim report for details on which signals were trimmed).

Solution

This is fixed in the latest 3.3i ChipScope release.
AR# 11265
Date Created 08/29/2007
Last Updated 06/10/2002
Status Archive
Type ??????