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AR# 11304

3.3i CORE Generator - Configuration statement error occurs when loading a design with a COREGen component in timing simulation. (VHDL)


Keywords: CORE Generator, COREGen, configuration, statement, timing, error, simulation, VHDL, 3.1i, 3.2i

Urgency: Standard

General Description:
A configuration loads successfully in functional simulation and the CORE Generator component is bound to my design; however, the timing simulation issues a configuration statement error. Why?


The configuration statement is only needed to bind the VHDL CORE Generator component in functional simulation.

Therefore, if the same testbench is being used for functional and timing simulation, the testbench entity (instead of the configuration) should be loaded in the simulator. The configuration can be commented out before compiling the files for timing simulation.
AR# 11304
Date Created 08/29/2007
Last Updated 11/13/2002
Status Archive