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AR# 11315

3.1i CORE Generator - Generation of cores from ISE causes "Error line 26: Pins only allowed on primary grids"


Keywords: core, CORE Generator, COREGen, ISE, schematic, ASY, .asy, symbol, primary, grids, Project Navigator

Urgency: Standard

General Description:
When I attempt to generate a CORE Generator core from an ISE project, the following errors are reported:

Errors or warnings compiling d:\customers\testfifo2\testressxg.asy.

Error line 26: Pins only allowed on primary grids.
Error line 30: Pins only allowed on primary grids.
Error line 34: Pins only allowed on primary grids.


This problem is seen on several cores that came from CORE Generator when it was invoked from ISE Project Navigator. (The problem does not exist when CORE Generator is invoked in stand-alone mode.)

This problem is generated from bad .asy file that is being used for schematic symbol generation. ISE projects try to generate the symbol, whether it is needed it or not. Therefore, if you are not performing an ISE-Schematic (ECS) flow or ISE-Foundation Schematic flow, this error can be ignored. All the necessary files should be created.

If you are performing an ISE-Schematic (ECS) flow, use the work-around described in (Xilinx Answer 9910).

If you are performing an ISE- Foundation Schematic flow, use the <core>.edn from your Schematic tool and run the Automatic Symbol Generation tool.

This problem was fixed in ISE 4.1i, which was released in September, 2000. If you are still experiencing this error with the 4.1i tool, please contact the Xilinx Hotline at:
AR# 11315
Date Created 04/02/2001
Last Updated 08/23/2002
Status Archive
Type General Article