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AR# 11331

3.x FPGA Express - What is a MUX_OP, and how do I know if I need one? (HDL-380 through 385)


Keywords: MUX, MUX_OP, MUXF5, MUXF6, MUXF7, MUXF8, HMAP, FMAP, multiplexor

Urgency: Standard

General Description:
What is a MUX_OP, and how do I know if I need it?



This information is taken from an application note on the Synopsys web site. If you are registered with Synopsys, please visit the "FPGA Synthesis" section on their web site to read the application note in its entirety.

The MUX_OP is a Synopsys "gtech" (generic technology) primitive that is inferred during elaboration. During optimization, the MUX_OP will be translated to the available multiplexor primitives in the target hardware (XC4000 series or Virtex series). A MUX_OP will be inferred under the following conditions:

- There are at least 4 inputs.
- There are no more than 256 outputs.
- At least 75% of the case statements are specified.
- There is only 1 arithmetic-type operator.

FPGA Express will not infer a MUX_OP when more than one arithmetic operator is used in order to allow efficient resource-sharing.

When a MUX_OP is inferred, the XC4000 series architecture will use FMAPs and HMAPs, and the Virtex series will use the special "mux"-type primitives.

You can override FPGA Express not inferring the MUX_OP by using the "infer_mux" attribute (as long as 50% of the cases in the case statement are specified). The HDL below demonstrates MUX_OP use by having more than one arithmetic operator:

VHDL example:

library ieee;
library synopsys;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use synopsys.attributes.all;

entity mux_8to1 is
port (a, b, c, d, e, f: in std_logic_vector (1 downto 0);
sel : in std_logic_vector (2 downto 0);
mux_out: out std_logic_vector (1 downto 0));
end mux_8to1;

architecture mux_8to1_arch of mux_8to1 is
process (a, b, c, d, e, f, sel) begin

-- remove the 'synopsys infer_mux' comment
-- to not infer a MUX_OP

case sel is -- synopsys infer_mux
when "000" => mux_out <= a + b;
when "001" => mux_out <= a + c;
when "010" => mux_out <= d - e;
when others => mux_out <= d - f;
end case;
end process;
end mux_8to1_arch;


Verilog example:

module mux_8to1 (a, b, c, d, e, f, sel, mux_out);

input a, b, c, d, e, f;
input [2:0] sel;
output [1:0] mux_out;

reg [1:0] mux_out;

always @(a or b or c or d or e or f or sel)

// remove the 'synopsys infer_mux' comment
// to not infer a MUX_OP

case (sel) // synopsys infer_mux
3'b000 : mux_out <= a + b;
3'b001 : mux_out <= a + c;
3'b010 : mux_out <= d - e;
default : mux_out <= d - f;

AR# 11331
Date Created 04/09/2001
Last Updated 08/11/2003
Status Archive
Type General Article