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AR# 11344

UniSim - Variables passed to GENERICs in functional simulation are not working properly (VHDL)

Description

The values passed to the GENERICs in the VHDL UniSim library are not working properly. No warning is issued, and the results are inconsistent.

Solution

Please note that the variable values are case-sensitive.  

 

The values of the GENERICs of type STRING in the Xilinx UniSim VHDL library are in capital letters. Consequently, if the values passed to the model are not capitalized, the model does not work as expected. For example, the following instantiation of the DCM works properly: 

 

component DCM 

--synopsys_translate_off 

generic (  

CLKOUT_PHASE_SHIFT : string := "FIXED"; -- Note the use of CAPITALIZATION here. 

DSS_MODE : string := "NONE"; 

STARTUP_WAIT : boolean := false; 

PHASE_SHIFT : integer := 200 ; 

);  

--synopsys_translate_on 

port ( CLKIN : in std_logic; 

CLKFB : in std_logic; 

DSSEN : in std_logic; 

PSINCDEC : in std_logic; 

PSEN : in std_logic; 

PSCLK : in std_logic; 

RST : in std_logic; 

CLK0 : out std_logic; 

CLK90 : out std_logic; 

CLK180 : out std_logic; 

CLK270 : out std_logic; 

CLK2X : out std_logic; 

CLK2X180 : out std_logic; 

CLKDV : out std_logic; 

CLKFX : out std_logic; 

CLKFX180 : out std_logic; 

LOCKED : out std_logic; 

PSDONE : out std_logic; 

STATUS : out std_logic_vector(7 downto 0) 

); 

end component; 

 

However, the following instantiation does not work properly: 

 

component DCM 

--synopsys_translate_off 

generic (  

CLKOUT_PHASE_SHIFT : string := "Fixed"; -- Note the use of lower-case letters here. 

DSS_MODE : string := "NONE"; 

STARTUP_WAIT : boolean := false; 

PHASE_SHIFT : integer := 200 ; 

);  

--synopsys_translate_on 

port ( CLKIN : in std_logic; 

CLKFB : in std_logic; 

DSSEN : in std_logic; 

PSINCDEC : in std_logic; 

PSEN : in std_logic; 

PSCLK : in std_logic; 

RST : in std_logic; 

CLK0 : out std_logic; 

CLK90 : out std_logic; 

CLK180 : out std_logic; 

CLK270 : out std_logic; 

CLK2X : out std_logic; 

CLK2X180 : out std_logic; 

CLKDV : out std_logic; 

CLKFX : out std_logic; 

CLKFX180 : out std_logic; 

LOCKED : out std_logic; 

PSDONE : out std_logic; 

STATUS : out std_logic_vector(7 downto 0) 

); 

end component; 

 

Consequently, you must ensure that all values passed to the GENERICs of type STRING in the Xilinx UniSim library are capitalized.

AR# 11344
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article