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AR# 11346

Project Navigator - Creating a schematic symbol causes "ERROR: This design does not contain an entity named main..."

Description

When I create a schematic symbol from a VHDL source in Project Manager, the following error occurs ("main" is the VHDL and entity name, and "FD" is a component instantiated in "main"):

Loading the object file C:\Xilinx\data\vhdlan\xc\virtex_macro_comp.vao...

R: VHDL Analyzer detecting a syntax error. Description of the error is:

main.vhd(19): Syntax error at or near: FD

Please correct this syntax error and try again...

ERROR: This design does not contain an entity named main...

vhdtdtfi completed with errors...

Done: failed with exit code: 0001.

Solution

This problem occurs when the component is not created completely in VHDL-87 syntax or completely in VHDL-93 syntax. 

In the VHDL-93 example below, the "is" at the end of the first line and the component name (FD) at the end of the last line are optional.

However, if one but not the other is used, the "Create Schematic Symbol" process reports the error:

VHDL-87 Example:

component FD

port (D : in std_logic;

C : in std_logic;

Q : out std_logic);

end component;

VHDL-93 Example:

component FD is

port (D : in std_logic;

C : in std_logic;

Q : out std_logic);

end component FD;

This is a problem with the VHDL analysis in the "Create Schematic Symbol" process only.

It does not affect standard VHDL synthesis.

Either include both the "is" at the end of the first line and the component name at the end of the last line, or omit both when you create schematic symbols from a VHDL source.

AR# 11346
Date Created 04/10/2001
Last Updated 09/24/2015
Status Active
Type General Article
Tools
  • ISE