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AR# 11348

12.1 Constraints Editor - Differential clock input does not appear as a "Clock Pad Net"

Description

When I use the Constraints Editor to place an "OFFSET IN BEFORE" or "OFFSET OUT AFTER" constraint on a group of registers or pads with respect to a differential clock input pad, the differential clock input pad does not appear in the "Relative to Clock Pad Net" pull-down menu (that is, the "OFFSET IN BEFORE" and "OFFSET OUT AFTER" constraints cannot be set through the Constraints Editor with respect to differential clock inputs).

Solution


This is a limitation of the Constraints Editor. To work around the problem, you must manually set the constraint in the UCF file.
For example:
The following setup is used for a differential clock input:
diff_clk_in_P -->|
| - IBUFGDS_LVPECL_33 ----> clk_in
diff_clk_in_N -->|
where:
diff_clk_in_P is the P-side differential clock input signal
diff_clk_in_N is the N-side differential clock input signal
IBUFGDS_LVPECL_33 is the differential clock input buffer
clk_in is the single-ended clock output from the differential clock buffer
To set an "OFFSET IN BEFORE" constraint on a hypothetical group of input pads named input_pads_grp, use this syntax:
TIMEGRP "input_pads_grp" OFFSET = IN 20 ns BEFORE "diff_clk_in_P";
NOTES:
1. The TNM group "input_pads_grp" must be defined in the UCF file before the "OFFSET IN BEFORE" constraint is specified.
For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf
AR# 11348
Date Created 08/29/2007
Last Updated 05/13/2012
Status Active
Type Known Issues
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
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