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AR# 11372

6.1i/5.1i SimPrim - The CLKDLL and DCM output signals do not appear to be aligned in timing simulation (VHDL, Verilog)

Description

Keywords: back-annotated, problem, skew aligned, CLK0, CLKFX, CLKDV

Urgency: Standard

General Description:
The output signals of the CLKDLL and DCM do not appear to be aligned with each other in timing (post-PAR) simulation. For example, the rising edge of CLK0 is not synchronized with the rising edge of CLK2X or CLKDV (in "Divide by 2" mode).

Why is this happening?

Solution

This problem is due to the way the simulators annotate the timing delays passed down by the SDF file. Depending on the input clock frequency and the delays in the device, the signals might or might not appear to be properly aligned.

To verify that the CLKDLL/DCM model is functionally correct, the simulation can be run for a short period of time without the SDF delays annotated; this will show whether the signals have lined up properly.

For more details on the skew problem in timing simulation, see (Xilinx Answer 11067).
AR# 11372
Date Created 04/13/2001
Last Updated 03/05/2006
Status Archive
Type General Article