UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11400

Foundation ISE3.1i ECS - When I create a macro, " Vhdl ( top.sch ) ERROR: Missing pin for I/O marker on net d(0)" occurs in the Design Flow

Description

Keywords: Foundation, ISE, 3.1i, macro, schematic, I/O, marker, pin

Urgency: Standard

General Description:
I am creating a macro in a schematic design (from "Create Schematic Symbol") for simulation purposes in Foundation ISE 3.1i. After elaborating certain changes on the schematic without updating it, the following error message is reported when I select <Check Design Rules>:

" Vhdl ( top.sch ) ERROR: Missing pin for I/O marker on net d(0)".

Solution

1

To avoid this error, you must update the macro by double-clicking on <Create Schematic Symbol>. A window will appear, warning that the symbol has already been created. Select "OK" to overwrite it.

2

Make sure that there are no .sym files for the top level file.
AR# 11400
Date Created 04/18/2001
Last Updated 08/15/2002
Status Archive
Type General Article