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AR# 11422

3.1i Virtex-II PAR - Placer ignores LOC constraints on IOBs.

Description

Keywords: PAR, constraint, Virtex-II, clock, IOB, PCF, ignore, place

Urgency: Hot

General Description:
My Virtex-II design appears to pass Place and Route successfully, but ends up with IOB placements that conflict with the LOC constraints in the PCF file.

This can be checked by loading the design in FPGA Editor with the PCF file and looking for messages of this type:

Resolved that IOB <Clk> must be placed at site F13.
Unplacing IOB Clk from site D11.
Unplacing IOB TXCLK from site F13.

The problem is related to the fact that some of the clock components were not LOC'd. (An algorithm that optimizes clock
placement was violating the LOC constraints.)

Solution

This problem will be fixed in version 4.1i, which is currently scheduled for release in August, 2001.

Until then, this problem can be avoided by making sure that all clock components (BUFGMUX's and DCMs) are LOC'd.
AR# 11422
Date Created 08/29/2007
Last Updated 10/22/2008
Status Archive
Type General Article