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AR# 11537

6.1i/5.1i UNISIMS - Setting the CLKDLL/DCM DIVIDE property to values other than "2" is unsuccessful (VHDL)

Description

Keywords: ModelSim, CLKDLL, CLKDV_DIVIDE, attribute, Functional, Simulation, UniSim

Urgency: Standard

General Description:
When I try to simulate the clock divide function of a DCM/DLL using a divisor other than 2, the simulator still shows the incoming clock signal as being divided by 2.

Solution

For VHDL, make sure that the CLKDV_DIVIDE mapping is included in the GENERICS part of the CLKDLL component declaration.

For example:

component CLKDLL
generic (
CLKDV_DIVIDE : real := 8.0
);
port(
clkin: in STD_LOGIC;
clkfb: in STD_LOGIC;
rst: in STD_LOGIC;
clk0: out STD_LOGIC;
clk90: out STD_LOGIC;
clk180: out STD_LOGIC;
clk270: out STD_LOGIC;
clk2: out STD_LOGIC;
clkdv: out STD_LOGIC;
locked: out STD_LOGIC
);
end component;

AR# 11537
Date Created 08/29/2007
Last Updated 10/16/2008
Status Archive
Type General Article