UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11614

3.x FPGA Express - FPGA Express does not synthesize comparators correctly

Description

Keywords: FE, FPGA Express

Urgency: Standard

General Description:
FPGA Express synthesizes the following comparator incorrectly:

DOUT <= '1' when (DIN_A) > (DIN_B & "111111111111111111") else '0';

(If the bit width is narrow, this should not be a problem.)

Solution

Please compare upper bits.

If you are using Virtex, Virtex-E, or Spartan-II, you may use the comparator that is available in CORE Generator.
AR# 11614
Date Created 05/16/2001
Last Updated 08/11/2003
Status Archive
Type General Article