We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11628

4.1i HDL Bencher - Can I use HDL Bencher on a design with multiple clocks?


Keywords: HDL Bencher, simulation, testbench, multiple, clock, VHDL, Verilog, time, edge

Urgency: Standard

General Description:
4.1i HDL Bencher only allows one clock source when performing clock timing. How can I generate a testbench that includes a second, third, or higher number of clocks?



When the other clocks are even multiples of one clock:

Use clock timing, and choose the fastest clock as the original clock. Then use the pattern wizard to toggle the other clocks every "X" cycles.

For example, if the original clock is 100 MHz, you can use the pattern wizard to toggle clock2 every 2 cycles; therefore, clock2 will be 25 MHz.


When the clocks are independent of each other:

Use combinatorial timing rather than clock timing. Make sure to choose the right precision for the time scale so that all the clocks can toggle at the needed frequencies.


5.1i HDL Bencher does allow for multiple clocks. The user is allowed to define which signals are defined as clocks and then associate the remaining signals with a specific clock.
AR# 11628
Date Created 05/17/2001
Last Updated 08/11/2003
Status Archive
Type General Article