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AR# 11680

SYNPLIFY - How do I disable the insertion of BUFs on high fanout lines?

Description

Keywords: BUF, Synplify, insert, insertion

Urgency: Standard

General Description:
By default, Synplify will insert BUFs on high fan-out lines in an effort to improve timing of the design.

How do I disable the insertion of BUFs on high fanout lines?

Solution

1

Use the syn_keep attribute to preserve all connections through synthesis.

Verilog

module example (<port list>);

wire [7:0] temp /* synthesis syn_keep = 1 */;

2

VHDL

library synplify;
use synplify.attributes.all;

entity example is
port ( <port list> )
end entity;

architecture XILINX of example is

signal temp : bit_vector (7 downto 0);
attribute syn_keep of temp : signal is true;
AR# 11680
Date Created 05/25/2001
Last Updated 04/20/2007
Status Archive
Type General Article