| AR# |
11713 |
| Part |
HW-SelectIO |
| Last Modified |
2008-10-09 00:00:00.0 |
| Status |
Active |
| Keywords |
Virtex-II, switch, simultaneous, SSO, outputs, Virtex-E, guideline, Virtex-II Pro, Pro, recommendation |
Description
Keywords: Virtex-II, switch, simultaneous, SSO, outputs, Virtex-E, guideline, Virtex-II Pro, Pro, recommendation
What are the simultaneously switching outputs (SSO) guidelines for Virtex-E, Virtex-II, and Virtex-II Pro devices?
Solution
For a detailed discussion about handling SSOs, please refer to (
Xilinx XAPP689),
Managing Ground Bounce in Large FPGAs. The SSO guidelines pointed to below are to be used in conjunction with the methodology outlined in the Application Note.
Virtex-II ProRefer to the
Virtex-II Pro and Virtex-II Pro X FPGA User Guide at:
http://www.xilinx.com/support/documentation/user_guides/ug012.pdfSee Simultaneous Switching Guidelines, page 201. Table 3-36 lists the maximum number of simultaneously switching outputs per Power/Ground pin pair.
Virtex-IIRefer to the
Virtex-II Platform FPGA User Guide at:
http://www.xilinx.com/support/documentation/user_guides/ug002.pdfSee Simultaneous Switching Output (SSO) Guidelines, page 188. Table 3-36 lists the maximum number of simultaneously switching outputs per Power/Ground pin pair.
Virtex-ERefer to the Detailed Functional Description data sheet at:
http://www.xilinx.com/support/documentation/data_sheets/ds022-2.pdfSelect Using Select I/O -> Design Considerations -> Simultaneous Switching Guidelines.
NOTE: The SSO guidelines for HSTL18 ( HSTL with VCCO = 1.8V) are not yet listed. For now, use the regular HSTL (with VCCO = 1.5V) guidelines and reduce by 25%. For more information on HSTL 1.8V support, refer to
(Xilinx Answer 9762).