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AR# 11719

6.1i CORE Generator, SIMPRIM - Problem seen during back-end simulation of Pos-Phy Level 3 and FlexBus-4 COREGen models (VHDL)

Description


General Description:

During the back-annotated (timing) simulation of a design containing the Pos Phy Level 3 Core or the FlexBus-4 Core, I encounter setup violations.

Solution


These cores use asynchronous clocks. Some setup violations can be expected when crossing clock domains using the current simulation models. (The models will be fixed in a future release.)



The present work-around is to turn off the timing checks on either the entire design or just the Block RAM instances.



To turn off the timing checks globally, use the +notimingchecks switch in the MTI VSIM command line or the Verilog-XL/NC-Verilog command line.



To turn off the timing checks on just the Block RAM instances, add a generic map to the RAMB4* and RAMB16* instances in the back-annotated netlist produced by Xilinx as follows:



1. Search for the Instances for "X_RAMB4" and "X_RAMB16" in the netlist.

2. Each X_RAM* instance will start off as follows:



X_RAMB16_S36_S36

generic map (

INIT_A => X"000000000",

INIT_B => X"000000000",

......



3. For each instance, add a new line for "timingcheckson", as illustrated below:



X_RAMB16_S36_S36

generic map (

timingcheckson => false, -- NEW GENERIC MAP ADDED

INIT_A => X"000000000",

INIT_B => X"000000000",

.....



This attribute turns timing checks off for the specific instance.
AR# 11719
Date Created 08/29/2007
Last Updated 07/28/2010
Status Archive
Type General Article