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AR# 11747

9.1i PLACE - "ERROR:Place:1721- The current designer-locked placement of the IOB xx and yy makes this design unroutable due to a physical routing limitation..."

Description

Keywords: place, 1721, clock, DDR, ERROR:Place:17, ERROR:Place:1721

A PAR result reports the following error:

"ERROR:Place:1721 - The current designer locked placement of the IOBs GLOBAL_RESET and MC_MC_IN(1) makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing with this design, please unlock or move one of these IOBs to a new location."

or:

"ERROR:Place:17 - The current designer locked placement of the IOBs dimm1_dq_io<38> and dimm1_dqs_out<13> makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing with this design, please unlock or move one of these IOBS to a new location."

What is wrong with the design?

Solution

1

This error describes an unroutable condition that occurs when two adjacent paired IOBs contain registers, often Dual Data Rate (DDR) flip-flops that do not share the same clock signals on their clock pins: ICLK1, ICLK2, OTCLK1 and OTCLK2, which use a shared routing resource.

In Virtex-II, the IOBs are in groups of four, as illustrated in the following figure:

A group of 4 IOBs
A group of 4 IOBs


Each IOB group has a switch matrix that feeds signals from the CLB fabric to these IOBs. The routing resources from the switch box to the clock pins are shared for IOB pairs. For this reason, the pairs of adjacent IOBs must share the same clock inputs for a given pin usage. When DDR FFs are used, the adjacent IOBs must therefore share the same two clock signals for the same clock pins. The following FPGA Editor figure illustrates the connection for one pair of IOBs:

Clock routing for an IOB pair
Clock routing for an IOB pair


The line highlighted in red is the shared clock input of the IOB pair. Consequently, each pair (the top and bottom pair as viewed in FPGA Editor) can have only two input clocks routed to it, using the ICLK1 and ICLK2 pins. For the same reason, each pair can have only two output clocks connected to the OTCLK1 and OTCLK2 pins.

You can use the FPGA Editor to see which pins share clock resources. When you open a design in FPGA Editor and look at the ICLK pins on the top or bottom two IOBs, you can see that the clock inputs for both IOBs come from the same output of the switch matrix (make sure "local lines" and "pin wires" are turned on). The IOB pairing is identical to the LVDS IOB pairing. Therefore, the package pin-out table can also be used for pin assignment to avoid conflict. For Virtex-II Pro, this is generally the case, but there are exceptions. See (Xilinx Answer 18780) for details.

The most common design errors leading to this placement error are:

- Multiple FFs are constrained to an IOB pair that use either more than two input clocks or more than two output clocks, when only two shared routing resources are available for each.

- An IOB containing DDR that has the same clock signal on both clock pins (one inverted internal to the IOB) is paired with an IOB that does not use the same clock signal.

In some cases, one of the registers involved is not required to be packed into the IOB. In that case, the problem can be avoided by applying the following constraint in the UCF file:

INST "ff_name" IOB = FALSE ;

If the IOB register pack is not optional, it is necessary to change the pin location assignments.

2

In some cases, the placement that causes the error should be routable. However, the incorrect flip-flop is used in one of the IOBs, and this makes the clock unroutable.

MAP supports the use of a BEL constraint in IOBs, enabling you to control which FF is used in the IOB and, where possible, enabling you to avoid clock conflicts in non-DDR registers. Valid values for the BEL constraint are: IFF1, IFF2, OFF1, OFF2, TFF1, and TFF2. The following is an example of a UCF constraint:

INST "ff_inst" bel = IFF1 ;

3

The problem described in (Xilinx Answer 18780) is also known to cause this problem in some IOB tiles located next to DCMs in Virtex-II Pro devices. The environment variable listed in that Answer Record will also correct this problem. If MAP has been run with the timing driven option (-timing), it will also be necessary to rerun MAP after setting the variable, before proceeding to PAR.
AR# 11747
Date Created 08/29/2007
Last Updated 10/13/2008
Status Active
Type General Article