UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11774

LogiCORE Viterbi Decoder v1.0 - 4.1i CORE Generator In a Viterbi Decoder core behavioral simulation, the "rdy" signal goes high one clock early

Description

Keywords: FEC, forward error correction, Viterbi

Urgency: Standard

General Description:
In a parallel Viterbi decoder, when c_has_nd = 0 and c_has_rdy=1, the rdy signal goes high one clock too early in the behavioral model.

The signal subsequently remains high in both the structural and behavioral code.

Solution

This is a behavioral model problem only, and the core implementation will work properly. Our developers are aware of the simulation mismatch and are working on a fix.

If you cannot work around this, you can perform a gate-level simulation of the core using the EDIF netlist; do this by taking the EDIF netlist for the core through NGDBuild, then running NGD2VHDL. For more information on this process, please refer to (Xilinx Solution 8065).
AR# 11774
Date Created 08/29/2007
Last Updated 03/14/2008
Status Archive
Type General Article