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AR# 11839

6.1i CORE Generator - BitGen DRC warning: "DesignRules:331 - Blockcheck: Dangling F output. F of comp afifo/BU75/SP is configured, but output is not used."

Description

General Description 

When running the bit stream generation (BitGen) of the Xilinx Implementation tool for a Virtex-II design, a warning message similar to the following might be reported: 

 

"Running DRC. 

WARNING:DesignRules:331 - Blockcheck: Dangling F output. F of comp  

fred/BU75/SP is configured, but output is not used. 

WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp  

fred/BU75/SP is configured, but output is not used."

Solution

If these components are coming from the asynchronous FIFO generated from CORE Generator, these messages can be safely ignored.  

 

These warnings are caused by the RAM16x1D primitives that are used for asynchronous FIFOs. The warnings occur when the SPO output of this primitive is not used. To check for this, search for these components in FPGA Editor, and see if they are configured as dual-port RAM.

AR# 11839
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article