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AR# 11846

3.1i CORE Generator 3.1i_IP4 - SpeedWave 7.0 compilation of lfsr_v1_0.vhd file results in errors

Description

Keywords: CORE Generator, COREGen, SpeedWave, errors

Urgency: Standard

General Description:
When the lfsr_v1_0.vhd file is compiled with SpeedWave 7.0, the following error messages appear:

VHDL Compiler, Release 7.01
Copyright (c) 2001, Innoveda, Inc.
Working library XILINXCORELIB ".\xilinxcorelib.lib".

Compiling ".\src\xilinxcorelib\lfsr_v1_0.vhd" line 1...
Library synopsys.lib (logical name: "SYNOPSYS") opened implicitly. (libAccess/124)
Compiled entity XILINXCORELIB.DVUNIT_BHV

Compiling ".\src\xilinxcorelib\lfsr_v1_0.vhd" line 58...
ERROR[138]::File .\src\xilinxcorelib\lfsr_v1_0.vhd Line 191: Choice expression should be locally static.

Solution

1

If you are not using LFSR V1_0, (and do not intend to use it in the near future), you can remove the lfsr_v1_0.vhd file from the VHDL analyze order, and no compilation errors will occur.

If you decide to use the LFSR v1_0 core, you should be able to generate and implement it. However, you will not be able to perform behavioral simulation on this core. There is, however, an option to perform post-NGDBuild simulation. Please see (Xilinx Answer 8065) for more information.

2

If you would still like to be able to perform behavioral simulation on LFSR, follow this quick work-around:

1. Comment out lines 102-133 of lfsr_v1_0.vhd (the entire CASE statement from CASE to END CASE).

2. Replace it with the line: cur_state <= 0;

As this will completely break the functionality of the DATA_VALID and NEW_SEED outputs, the core must NOT be generated with either of these output ports present. This work-around should allow the code to compile by eliminating the problem CASE statement.

3

There is a problem in the lfsr_v1_0.vhd file that was not detected by MTI VHDL simulator. Currently, Xilinx only tests XilinxCoreLib with MTI Simulator; therefore, some problems may be detected if other simulators are used.

This problem is scheduled to be fixed in an upcoming IP update. However, since the IP developers do not currently have access to NC-VHDL, we cannot guarantee which IP update will contain the fix.

4

To work around this bug, you will have to create your own LFSR based on the Fibonacci implementation with XNOR feedback.
AR# 11846
Date Created 06/26/2001
Last Updated 08/23/2002
Status Archive
Type General Article