We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11874

6.1i TRCE - A path constrained by CLK is reported differently in the timing report and the timespec


A timing report on a design for one clock reports a path that is clocked from a different clock net. (This second clock net is independent from the first clock.)


In the 4.1i and newer software versions, if the clocks are independent, two clock period constraints are needed; the tools will not analyze between clock domains.

AR# 11874
Date Created 08/29/2007
Last Updated 01/18/2010
Status Archive
Type General Article