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AR# 11930

3.1i CORE Generator - "ERROR: Some initial values do not match either the Memory Initialization Radix or Data Width"

Description

Keywords: Distributed Memory, Dual Port Block Memory, Single Port Block Memory

Urgency: Standard

General Description:
COE files with decimal data and line feeds are not parsed properly for some cores; as a result, you may see the following error when loading a .coe file where the memory initialization values are being specified using a radix of 10, and the data are broken up into separate lines:

"ERROR: Some initial values do not match either the Memory Initialization Radix or Data Width. Press the Show Values button to view them."

The offending COE file looks like this:

memory_initialization_radix = 10;
memory_initialization_vector = 237 52 88 99 101 63 0 75
237 52 88 99 101 63 0 75
237 52 88 99 101 63 0 75
237 52 88 99 101 63 0 75
237 52 88 99 101 63 0 75
237 52 88 99 101 63 0 75
237 52 88 99 101 63 0 75
237 52 88 99 101 63 0 75;

There is a problem parsing linefeeds when the radix is 10. This issue occurs in the following cores:

Distributed Memory v4.1
Dual Port Block Memory v3.1
Single Port Block Memory v3.1

For the Distributed Memory core, if you click on "Show Coefficients" (not "Show Values" as indicated by the message), you will see that the last value in each line of data is concatenated with the first number in the next line. This leads to a corrupted value (75237) that exceeds the data width of 16.

Solution

To work around this problem, merge all data values in the memory_initialization_vector line into a single line.

This problem has been fixed in 4.1i IP Update #1, available at:
http://www.xilinx.com/ipcenter/coregen/updates.htm

You must have 4.1i Xilinx Implementation Tools to use the 4.1i IP update.
AR# 11930
Date Created 07/11/2001
Last Updated 08/23/2002
Status Archive
Type General Article