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AR# 11936

Virtex-II - What is the minimum granularity for DCM phase shift? How does this affect phase shift?


What is the minimum granularity for DCM phase shift?

What is the minimum phase shift at a given frequency?

How does this affect phase shift in my design?


The minimum granularity is the greater of two limiting factors:

1. The minimum phase shift step size = 1/256 x CLKIN_Period.

2. The tap delay resolution (DCM_TAP). The specifications for DCM_TAP_MIN and DCM_TAP_MAX are available in the Virtex-II Data Sheet, under Miscellaneous Timing Parameters. See http://www.xilinx.com/support/documentation/data_sheets/ds031.pdf

Therefore, assuming a typical DCM_TAP of 45 ps, at ~90 MHz with an 11.11 ns period, the 1/256 x CLKIN_Period is ~45 ps.

1. At a frequency < approx. 90MHz:, 1/256 x CLKIN_Period > 45 ps; hence the minimum step size is limited by #1 above.

2. At a frequency > approx. 90MHz, 1/256 x CLKIN_Period < 45 ps; hence the minimum step size is limited by #2 above.

How does phase shift work at frequencies greater than 90 MHz?

At any condition, regardless of the CLKIN frequency, the PHASE_SHIFT (PS) value is determined by the following equation:

"desired phase shift" = (PS/256) * (CLKIN period).

From this PS value, the DPS function of DCM will select the appropriate tap setting. This tap setting will vary across process, voltage, and temperature (PVT).

For example, if CLKIN = 150 MHz (6.67 ns period), and the "desired phase shift" = 680 ps:

0.680 = PS/256 * 6.67

PS = 26

You would enter this as the PHASE_SHIFT value.

The DCM_TAP of ~45 ps is only an approximation. The actual tap value can range from 30 ps to 60 ps at any given time, depending upon PVT. Hence, 10 tap steps does not always mean 10 * 45 ps = 450 ps. In addition, the DCM might not adjust to a new phase shift at every 1/256 phase shift increment if 1/256 x CLK_Period < DCM_TAP, as 1/256 is not equal to 1 tap.

For example, when you change the PS value from "3" to "4", the DCM may not increment the phase shift if the current phase shift is closer to the ideal value when compared to the next tap at the PVT.

In this case, the design consideration is that at any time the DCM will find the closest phase shift given the PHASE_SHIFT attribute value. The error at this PHASE_SHIFT for a simple case of using CLK0 will be CLKOUT_PER_JITT_0 + CLKIN_CLKFB_PHASE. These values are specified in the Virtex-II Data Sheet (http://www.xilinx.com/support/documentation/data_sheets/ds031.pdf).

The DCM_TAP value is included in the output jitter specs along with random jitter introduced by the DCM and by the FPGA. Using a FIXED phase shift will allow the design to be within 5-10% of the desired phase shift point. If more accuracy is needed, use the VARIABLE mode to dial it in.

AR# 11936
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article