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AR# 11980

3.x FPGA Express - Inverters are not being preserved in the proper hierarchy


Keywords: invert, hierarchy, FPGA, Express, compiler, II, BLIS

Urgency: Standard

General Description:
When "preserve hierarchy" is selected with hierarchical design signals that are inverted before being mapped to a lower-level module/component, the post-synthesis lower-level module/component may contain the inverter.


The "preserve hierarchy" function still allows inverters and buffers to move around in the design.

To prevent inverters and buffers from moving around in the design, use the block-level incremental synthesis (BLIS). For more information about BLIS, please refer to the FPGA Express online help: Help Topics -> Application Notes -> General Methodology -> Using Block-Level Incremental Synthesis.
AR# 11980
Date Created 07/18/2001
Last Updated 08/11/2003
Status Archive
Type General Article