How does a DDR MUX in the DDR register work? Can I switch from one flip-flop to the other without causing glitches?
It appears that the FDDRxxx primitive is not needed for input DDR registers. Is there a primitive that I can use, or are the input DDR flip-flops only inferred? For outputs, I instantiate the FDDRxxx register and the proper OBUF; can I do the reverse for inputs?
The dual data rate primitives in Virtex-II/-II Pro devices are available in the IOB only:
- For input, instantiate the IFDDR* component.
- For output, instantiate the OFDDR* component.
Please see the "Libraries Guide" for more information on the usage and instantiation templates of these primitives:
In the "Libraries Guide" , select the device family you are intested in (i.e., Virtex-II) and go to "Design Elements". Then select the desired DDR component (e.g., IFDDRCPE).
The DDR registers and MUX are part of the same circuit. This is achieved by using two master latches (for incoming data paths) and one slave latch for the output. All paths (data and clocks) are very carefully delay-matched.
The critical information regarding this issue is as follows:
1. Because all path data and CLKs are very carefully balanced, duty-cycle degradation will not occur and there is no chance of glitches.
2. There is no difference in the paths for SDR and DDR since a single FF usage will still go through the master and slave. This is why there is only one specification for the IOB register (no special parameter for DDR).