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AR# 12018

4.1i CORE Generator - Virtex and Virtex-II COREGen adds BUFG for a clock signal when the "Add Pad" feature is used.


Keywords: CORE Generator, COREGen, Virtex, Virtex-II, IBUF, BUFG, NGDBuild, MAP, MapLib:32

Urgency: Standard

General Description:
When you run the 4.1i Implementation tool, the following MAP error is reported if you have a core module:

ERROR:MapLib:32 - LUT4 symbol "BU2" (output signal=N61) has an equation that uses an input pin connected to a trimmed signal. Make sure that all the pins used in the equation for this LUT have signals that are not trimmed (see trim report for details on which signals were trimmed).


In CORE Generator's main GUI, under Project Options -> Output Products, in the Elaboration Options section, there is an "Add Pad" feature. If "Add Pad" is selected, COREGen inserts BUFG for clock signals for Virtex and Virtex-II architectures instead of IBUFG. Since the required IBUFG is not attached to appropriate input clock signals, logic gets trimmed, resulting in the above MAP error.

The work-around for Virtex is to edit the EDIF netlist generated by CORE Generator, and replace all references to "BUFG" with "IBUFG". You may have several instances of clock, depending upon the core you are using.

For Virtex-II, an IBUFG must be followed by a BUFG, so you will need to insert an IBUFG before every instance of a BUFG, which can be a difficult thing to do. We recommend that you install E_IP1 and follow the work-around outlined in (Xilinx Answer 12757).

This problem is fixed for Virtex in 4.1i IP Update #1 (E_IP1).

For Virtex-II, the problem will be fixed in 4.1i IP Update #2 (E_IP2), which is scheduled for release in late February, 2002.
AR# 12018
Date Created 07/23/2001
Last Updated 09/11/2003
Status Archive
Type General Article