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AR# 12063

4.1 HDL Bencher - Back-annotated Verilog simulation fails for all synchronous elements that have a reset/preset


Keywords: post, translate, Verilog, simulation, GSR, initialize, Bencher

Urgency: Standard

General Description:
When I run a back-annotated Verilog simulation, all synchronous elements with a reset/preset will not initialize until the GSR signal is toggled.


In order for these elements to be initialized, the Global Set Reset (GSR) must be toggled at the beginning of the simulation; this will emulate the Power-On-Reset of the FPGA hardware.

To do this, add the following code to any Verilog test fixture:

reg GSR;
assign glbl.GSR = GSR;
initial begin
GSR = 1;
#100 GSR = 0;

(NOTE: The GSR port does not need to be added to the back-annotated simulation file.)

This information cannot be handled directly in HDL Bencher; you must generate the test fixture from the TBW source, the add the code to the test fixture.
AR# 12063
Date Created 07/25/2001
Last Updated 08/12/2003
Status Archive
Type General Article