We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12158

4.1i Virtex-II PAR - RLOC_ORIGIN for Virtex-II: RPMs should place a macro in the same slice type as the original macro origin


Keywords: RPM, macro, placer, placed, alignment, slice, RLOC_ORIGIN

Urgency: Standard

General Description:
Virtex-II RPMs appear to be placed incorrectly. In one example, an RPM that was intended to occupy a single row ended up occupying two rows.


This problem occurs when an RLOC_ORIGIN value is used that places the macro in a slice type (one of the four CLB slices, S0-S3) that does not correspond to the slice type of the RPM origin. In most cases, RPM macros are created with the S0 slice as the origin and should always be placed into an S0 slice type.

You can generally avoid this problem by designing RPMs with an X0Y0 slice as the lower-left corner, then applying an RLOC_ORIGIN to an S0 slice type.

A warning message is planned for the next major software release (after 4.1i) that will say:

WARNING: The RPM <RPM Name> with the RLOC_ORIGIN <RLOC_ORIGIN> was created with an origin aligned with SLICE <0|1|2|3> of the CLB. The RLOC_ORIGIN must maintain the positioning of the SLICES in a CLB exactly as they where when this RPM was created in order to guarantee the proper positioning of the logic in this RPM. This can cause placement, routing and/or timing issues for carry chains, F5, F6, F7, F8 muxes, distributed RAMs, etc.
AR# 12158
Date Created 08/29/2007
Last Updated 10/22/2008
Status Archive
Type General Article