UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 12173: 4.1i Trace (TRCE)/Timing Analyzer - An incorrect period requirement is used for cross-clock domain paths for multiple constraints

AR# 12173

4.1i Trace (TRCE)/Timing Analyzer - An incorrect period requirement is used for cross-clock domain paths for multiple constraints

Description

General Description:

An incorrect period value is used for paths that cross clock domains. (This only occurs if either the source or destination register is covered by multiple PERIOD constraints.) How do I avoid this?

Solution

You can avoid this situation by eliminating the extra PERIOD constraints.

This issue was fixed in the 4.2i software.

AR# 12173
Date 01/18/2010
Status Archive
Type General Article