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AR# 12265

4.1i Virtex-II PAR - Manual intervention to meet tight (1 ns) BLKRAM-->FF timing spec.


Keywords: BLKRAM, FF, flip-flop, register, path, timing, direct

Urgency: Standard

General Description:
A design was attempting to meet a very tight (1ns) timing spec on a 32-bit BLKRAM output bus to the slice flip-flop registering the outputs. Auto placement of the slices and initial attempts at manually constraining the slices resulted in more than half of the 32 paths failing with routing delays as high as 1.6 ns; this happened because many routes needed extra switchbox "bounces" to reach the slice pins, even though some were quite close.

An analysis of the "good" autoroutes revealed that these paths could meet timing if the router were able get through both switch boxes with a single connection and make use of the direct connections available between switch boxes. This limits the number of site pins that could be reached cleanly.



Examining the possible routing paths, three conclusions can be made:

1. Since there are dedicated switchbox paths to both BX and BY pins, it is important to balance the register utilization between the XQ and YQ slice bels.

2. Since there are switchbox-to-switchbox direct connections in both the left and right directions, it is important to balance the slice LOCs between CLBs on both the left and right sides of the BLKRAM.

3. Since the BLKRAM outputs are broken up into groups of eight pins per CLB row, the slice LOCs should also be partitioned into groups of eight per row.

The resulting LOC constraints that were chosen used:

1. Two flip-flops per slice;
2. Two slices per CLB (top, bottom);
3. Two CLBs per group of 8 BLKRAM outputs (left, right).

This configuration met the 1ns time spec on all 32 paths in a Virtex-II -4 part.

Example of UCF syntax for LOC of a single register:



A CR has been logged to investigate possible improvements to the automatic placement of this design.
AR# 12265
Date Created 08/29/2007
Last Updated 10/22/2008
Status Archive
Type General Article