We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12299

7.1i Timing Analzyer\TRCE - TRCE is erroneously reporting a single-phase clock as a two-phase clock


General Description:

My design uses a number of 3-state enable FFs in the IOBs, and I modified the design in FPGA Editor. The timing report states that two-phase clocks are used for several components that I modified. However, no two-phase clocks exist between these two components when they are analyzed in FPGA Editor. Why?


Timing Analyzer is reporting two-phase clocks because the NCD contains SuperBELs, and Timing Analyzer makes the worst-case assumption that the SuperBELs may invert clock signals (i.e., falling edge). The mapper creates the SuperBELs from hard macros, and FPGA Editor creates SuperBELS when the user modifies a component in the design.

To work around this issue, use FROM:TO constraints, rather than PERIOD constraints on those paths that are reported as two-phase clocks.

AR# 12299
Date Created 08/29/2007
Last Updated 01/18/2010
Status Archive
Type General Article