UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12386

4.1i BitGen - DRC Warning: "Designrules:331 - Blockcheck: Dangling XUSED output..."

Description

Keywords: BitGen, Designrules, DRC, blockcheck

Urgency: Standard

General Description:
BitGen issues a DRC Warning similar to the following:

WARNING:DesignRules:331 - Blockcheck: Dangling XUSED output. XUSED of comp UCORE/RBSAA/rb_gcr_map/bcsd_irq_src_sync(17) is configured, but output is not used.

Solution

This warning can be safely ignored in most cases. To be certain, check your design in FPGA Editor using the steps below. The warning message is typically issued because of an unusual, yet valid slice configuration.

To check this warning message:

1. Open the design in FPGA Editor.
2. Navigate to the offending slice. (The components are listed alphabetically in the component list on the right side of your screen in FPGA Editor.)
3. Double-click on the slice mentioned in the warning message. (For example, in the warning above, the slice would be UCORE/RBSAA/rb_gcr_map/bcsd_irq_src_sync(17).)

The warning may be ignored if the following criteria are met:

1. The F5 and X outputs are both in use.
2. The same signal name is shown on both of these outputs.

This configuration is not common, although it is perfectly legal. The XUSED component is the mux that drives the .X output from a slice.

If the above criteria are not met, please contact Xilinx Technical Support for assistance by opening a WebCase at:
http://support.xilinx.com/support/clearexpress/websupport.htm
AR# 12386
Date Created 08/29/2007
Last Updated 09/30/2005
Status Archive
Type ??????