Does the PL4 core support dynamic alignment and/or training patterns?
Versions 3.1 and earlier of the Xilinx PL4 core do not support dynamic alignment. For these versions, only static alignment is supported; therefore, you must lay out the board very carefully to ensure that signals arrive at the same time. Trace length consistency must be maintained. In version 3.x, the Xilinx PL4 core can transmit and receive training patterns; however, the core does not use the training patterns to bit-align the data to the clock.
Version 4.0 of the PL4 core does not support dynamic alignment.
Versions 5.0 and later of the PL4 core do support dynamic bit alignment, and the clock will be centered on each bit of the 16-bit bus. Please see the latest data sheet for more information: