This Answer Record contains a list of all known issues for SPI-4.2 (also known as POS-PHY Level 4 (PL4) v6.2).
The known issues in this Answer Record apply to both v6.2 and v6.1 of the SPI-4.2 Core. Subsequently, any Answer Records written for v6.1 of the SPI-4.2 apply to v6.2 of the Core.
The Known Issues are divided into the following sections:
- Constraints and Implementation
- General Simulation Issues
- Verilog Demonstration Testbench Simulation Issues
- Other Helpful Answer Records
V6.2 SPI-4.2 KNOWN ISSUES
Constraints and Implementation
- The SPI-4.2 v6.2 release is fully tested, and it supports ISE 6.3i (with the latest Service Pack and IP Update 4). If you are currently using ISE 6.1i or 6.2i, see the Required Software section of (Xilinx Answer 18896). If you are using ISE 7.1i, see (Xilinx Answer 20486).
- After installing v6.2 on to ISE6.3i, I cannot find v6.2 in the CORE Generator GUI listing . (Xilinx Answer 20595).
- Migrating SPI-4.2 Core from v6.0.1 to v6.2. (Xilinx Answer 18903)
- If you are implementing Dual SPI4.2 Core in a single FPGA, consult your local FAE or Xilinx Technical Support.
- SPI-4.2 signals are locked to specific I/O locations. Altering these pin locations is NOT recommended. (Xilinx Answer 18087)
- SPI-4.2 signals default to LVDS without the internal device termination. If internal termination is desired, this must be set in the UCF file. (Xilinx Answer 18089)
- TStat[1:0] signals use IBUFGDS when using LVDS status I/O. (Xilinx Answer 19105)
- TStat[1:0], TSClk, RStat[1:0], RSClk defaults to LVDCI_33 I/O Standards if they are not specifically defined. (Xilinx Answer 20527)
- When I run an implementation tool with an SPI-4.2 Core, several NGDBuild WARNING and INFO messages are reported. (Xilinx Answer 18927)
- Timing Analyzer (TRCE) reports "0 items analyzed". (Xilinx Answer 18928)
- When I run an implementation on a 2VP20-FG676, MAP reports an error. (Xilinx Answer 18998)
- When I run an implementation on a 2V3000-FF1152 Dynamic, PAR reports that one signal is not completely routed. (Xilinx Answer 18945)
- When I generate an SPI-4.2 (PL4) Core through CORE Generator, the following errors occur:
......."ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\5_2i\pl4_core.asy does not exist."
......."ERROR: Did not generate ISE symbol file for core <pl4_core>." (Xilinx Answer 15493)
- BitGen gives error on unrouted nets if MAP -timing is not used. (Xilinx Answer 19042)
General Simulation Issues
- Does the SPI-4.2 (PL4) Core have a required startup sequence or reset procedure? (Xilinx Answer 16176)
- When I simulate an SPI-4.2 (PL4) Source Core, glitches occur on TDat and TCtl. This is visible on gate-level simulation as well as in timing simulation. (Xilinx Answer 15579)
- When I simulate the SPI-4.2 Core, an unknown state or "x" appears on some of the signals. (Xilinx Answer 17686)
- Simulation of the SPI-4.2 (PL4) Core using dynamic alignment requires timing simulation to properly simulate the dynamic alignment per-bit de-skew capabilities of the Sink Core. (Xilinx Answer 15436)
- When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behavior occurs. (Xilinx Answer 15578)
- When running timing simulation in Verilog, you might see strange behavior such as the core never goes in frame, signals going "x," or pulses are swallowed. (Xilinx Answer 9872)
Verilog Demonstration Testbench Simulation Issues
- When I run a simulation on the Verilog demonstration testbench, "# RDat Info: Stimulus Module FIFO is empty, expect idles. <simulation time>" is reported. (Xilinx Answer 18938)
- When I run a simulation on the Verilog demonstration testbench, "# RStat Info: Sink is out of frame. Expect TDat mismatches. <Simulation Time>" is reported. (Xilinx Answer 18940)
- When I run a simulation on the Verilog demonstration testbench, "# Timing Violation Error : RST on instance pl4_demo_testbench.pl4...must be asserted for 3 CLKIN clock cycles" is reported. (Xilinx Answer 18941)
- When I run a simulation on the Verilog demonstration testbench, RDat becomes "x" and SnkFFPayloadErr is flagged. (Xilinx Answer 18987)
- When Fixed Static Alignment is used, it is necessary to determine the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations. (Xilinx Answer 16112)
- An SPI-4.2 (PL4) Sink Core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP4 error. (Xilinx Answer 15442)
Other Helpful Answer Records
- What is the power consumption of the v6.2 SPI-4.2 (PL4) Core? (Xilinx Answer 18936)
- Is a description of error and control signals available in addition to the information provided in the SPI-4.2 (PL4) Data Sheet? (Xilinx Answer 14968)
- How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM? (Xilinx Answer 15500)
SPI- 4.2 (PL4) v6.0/6.0.1 KNOWN ISSUES
The PL4 v6.0/6.0.1 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 18902) for information on existing PL4 v6.0/6.0.1 issues.
SPI- 4.2 (PL4) v5.2 KNOWN ISSUES
The PL4 v5.2 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 17664) for information on existing PL4 v5.0 issues.
SPI- 4.2 (PL4) v5.0 KNOWN ISSUES
The PL4 v5.0 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 16546) for information on existing PL4 v5.0 issues.
SPI- 4.2 (PL4) v4.0 KNOWN ISSUES
The PL4 v4.0 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 16331) for information on existing PL4 v4.0 issues.
SPI-4.2 (PL4) v3.x KNOWN ISSUES
The PL4 v3.x is no longer supported for new customers; please use the latest version of the core. For information on existing PL4 v3.x issues, see (Xilinx Answer 16332).