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AR# 12440

4.1i XST - XST does not respect register ranges declared in HDL (Naming conventions)

Description

Keywords: register, bus, array, index, range, preserve

Urgency: Standard

General Description:
XST will not preserve the bus/array numbering system as declared in the HDL code when the numbering does not begin at zero.

For example, an internal register that I declare as:

"signal tmp: std_logic_vector(7 downto 4) "

is represented in the final netlist as

"tmp(3 downto 0)"

Furthermore, an internal bus that I declare as:

"signal tmp: std_logic_vector(7 downto 0)"

will be represented in the final netlist as single nets:

"tmp_0, tmp_1, ..."

Solution

There is currently no known way to work around this issue.

NOTE: This problem has been fixed in the 5.1i version of XST.
AR# 12440
Date Created 08/30/2001
Last Updated 08/06/2003
Status Archive
Type General Article