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AR# 12479

4.1i Virtex-II MAP - "FATAL_ERROR:Ncd:basncsignal.c:282:1.28 - Could not find a bel for a signal on pin DIFFO_OUT of comp out..."

Description

Keywords: LVPECL, LVDS, Select I/O, MAP, PAD, OBUFDS

Urgency: Standard

General Description:
A differential output I/O standard is being applied to a PAD instance using the Constraints Editor instead of the more usual practice of applying it to the OBUFDS instance. (It should work on either.) The result is that MAP fails with the following error:

FATAL_ERROR:Ncd:basncsignal.c:282:1.28 - Could not find a bel for a signal on pin DIFFO_OUT of comp out. Its current programmed state is : OMUX:O1 O1INV:O1 IOATTRBOX:LVPECL_33. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com

(NOTE: This Answer Record is only a good match for your problem if the pin mentioned in the error message is named "DIFFO_OUT".)

Solution

1

This problem will be fixed in the next major software release.

Meanwhile, a differential output IOSTANDARD should be applied to the OBUFDS instead of the PAD.

2

VHDL Example (XST):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vhdl_lvpecl is
Port ( ina : in std_logic;
inb : in std_logic;
outa : out std_logic;
outb : out std_logic);
end vhdl_lvpecl;

architecture behavioral of vhdl_lvpecl is

component IBUFDS
port (
I : in std_logic;
IB : in std_logic;
O : out std_logic
);
end component;

component OBUFDS
port (
I : in std_logic;
OB : out std_logic;
O : out std_logic
);
end component;

attribute IOSTANDARD : string;
attribute IOSTANDARD of U0 : label is "LVPECL_33";
attribute IOSTANDARD of U1 : label is "LVPECL_33";

signal reg1: STD_LOGIC;

begin

U0: IBUFDS
port map(
I => ina,
IB => inb,
O => reg1
);

U1: OBUFDS
port map(
I => reg1,
O=> outa,
OB => outb
);

end behavioral;

3

Verilog Example (XST):

module io_test(in,out,inb,outb);

input in, inb;
output out, outb;

wire INT_SIG;

IBUFDS U1 (.I(in), .IB(inb), .O(INT_SIG));
OBUFDS U2 (.I(INT_SIG), .OB(outb), .O(out));

// synthesis attribute iostandard of U1 is LVPECL_33
// synthesis attribute iostandard of U2 is LVPECL_33

endmodule
AR# 12479
Date Created 09/05/2001
Last Updated 08/20/2003
Status Archive
Type General Article