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AR# 12483

3.6 FPGA Express - Bad logic is generated from shift operator ">>" on a parameter in Verilog

Description

Keywords: parameter, shift, Verilog, FPGA Express

Urgency: Standard

General Description:
FPGA Express generates bad logic when performing a part-select of a parameter whose type is not explicitly defined.

A simple test case is as follows:

module E (out);
output [2:0] out;
parameter p = (32'h20 >> 32'd2 );
assign out = p[3:1];
endmodule

Solution

This problem is fixed in the latest FPGA Express update with 4.1i Service Pack 2, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first FPGA Express version containing the fix is version 3.6.1.
AR# 12483
Date Created 09/05/2001
Last Updated 08/11/2003
Status Archive
Type General Article