We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 12490

Virtex-II - What is the CLKA -> CLKB clock-to-clock setup time of the block RAM (Tbccs)?


A value for Tbccs is specified in the data sheets for Virtex and Virtex-E devices. What is the value for the Virtex-II family? How do I calculate the value of Tbccs?


For an explanation of the "Tbccs" parameter, please see (Xilinx Answer 5894)


Tbccs is the same as the total block RAM minimum clock period (min pulse high + min pulse low) = (Tbpwh + Tbpwl).

AR# 12490
Date 05/08/2014
Status Archive
Type General Article