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AR# 12514

LogiCORE SPI-4.2 (POS-PHY L4) v3.x - Methods for clock reduction in the PL4 core


General Description:

The PL4 clock requires twelve clock buffers: six clocks and six additional clock inputs (SrcFFWClk, SnkFFRClk, RCalClk, TCalClk, TStatClk, and RStatClk.)

What can I do to reduce the use of clock buffers?


In many applications, shared clock resources can drive the six clock inputs. The following clocks are natural pairs, and in typical applications they can share a common clock domain:

SrcFFWClk and SnkFFRClk

RCalClk and TCalClk

TStatClk and RStatClk

Additionally, the core provides access to its internal clocks through the following outputs:

SysClk_GP -- 1/2 frequency of SysClk)

RDClk_GP -- 1/2 frequency of the PL4 bus input RDClk

RSClk_GP -- 1/4 of the RDClk)

TSClk_GP -- driven by PL4 bus input TSClk

Each of these clock outputs is driven by a global clock buffer. They can be connected to user logic or driven back into the core's clock input without using additional Virtex-II clock resources. Note that the appropriate signal inputs and outputs should be synchronized and sampled (respectively) with their associated clocks.

AR# 12514
Date Created 08/29/2007
Last Updated 05/03/2010
Status Archive
Type General Article