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AR# 12524

8.1i Virtex-II MAP - "WARNING:DesignRules:549 - Blockcheck: Unexpected DCM programming. For DCM comp "x", when the CLKFX or CLK180 pins are used, the CLKIN_PERIOD attribute must be specified..."

Description

When I run a design that uses the CLKFX output of the DCM through MAP, the following warning is reported: 

 

"WARNING:DesignRules:549 - Blockcheck: Unexpected DCM programming. For DCM comp clock/clk_62_5_dcm, when the CLKFX or CLKFX180 pins are used the CLKIN_PERIOD attribute must be specified in order to achieve optimal performance."

Solution

You must set the CLKIN_PERIOD in the netlist so that the timing tools know what period CLK will come out of this pin. The attribute is only available in nanoseconds and must be of type "string" in the netlist. 

 

UCF example

INST "foo/bar" CLKIN_PERIOD=35;  

 

Verilog example of instantiated DCM for Synopsys tools

 

DCM U_DCM (  

.CLKFB(CLK1X),  

.CLKIN(CLK_IN),  

.DSSEN(GND),  

.PSCLK(GND),  

.PSEN(GND),  

.PSINCDEC(GND),  

.RST(RST),  

.CLK0(CLK0_W),  

.LOCKED(LOCK) 

); 

 

// synthesis attribute declarations 

/* synopsys attribute  

 

DLL_FREQUENCY_MODE "HIGH" 

DUTY_CYCLE_CORRECTION "TRUE" 

CLKOUT_PHASE_SHIFT "VARIABLE" 

PHASE_SHIFT "10" 

STARTUP_WAIT "FALSE" 

CLKIN_PERIOD "16" 

*/ 

 

EDIF example

 

(instance clk_62_5_dcm (viewRef verilog (cellRef DCM)) 

(property LOC (string "DCM_X3Y1")) 

(property CLKIN_PERIOD (string "16")) 

(property CLKFX_MULTIPLY (integer 16)) 

(property CLKFX_DIVIDE (integer 15)) 

(property DFS_FREQUENCY_MODE (string "LOW")) 

(property DLL_FREQUENCY_MODE (string "LOW")) 

(property DUTY_CYCLE_CORRECTION (string "TRUE")) 

(property STARTUP_WAIT (string "FALSE"))

AR# 12524
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article