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AR# 12534

4.1i MAP - "ERROR:DesignRules:486 - Blockcheck: Invalid DCM feedback loop."

Description

Keywords: CLK0, DDR, drc, clock, forward, mirror

Urgency: Standard

General Description:
When I try to route the CLK0 output of a DCM to a clock input of a DDR rather than an output buffer, the following error is reported:

ERROR:DesignRules:486 - Blockcheck: Invalid DCM feedback loop. The signal CLKFB_w on the CLKFB pin of DCM comp U_DCM1 was driven by an IOB site but the signal loop could not be traced back to the CLK0 or CLK2X pin of comp U_DCM1. The signal out the CLK0 or CLK2X pin must drive an IOB input pin with programming out to the PAD.

Solution

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 4.1i Service Pack 1.

The error is now a warning.
AR# 12534
Date Created 09/11/2001
Last Updated 08/20/2003
Status Archive
Type General Article