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General Description: When I run a simulation, the following warning is reported:
CHAN_BOND_MODE is not in OFF,MASTER,SLAVE_1_HOP,SLAVE_2_HOPS.
In the VHDL simprim_SMODEL, the CHAN_BOND_MODE attribute is given in lower-case letters, but it is given in upper-case letters elsewhere. Since VHDL is not case sensitive, it compiles without errors. This will be seen in the UniSim SMODEL, as well.