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AR# 12576

Cadence Conformal - Support for the Xilinx/Conformal formal verification flow


General Description: 

How do I obtain technical support for the Verplex/Xilinx formal verification flow?


Xilinx supports gate (post-PAR) to gate (post-PAR) verification using the Conformal LEC tool. 


For any other verification (RTL to RTL, RTL to GATE, RTL to Post-Synthesis, Post-Synthesis to Gate), please contact Cadence to see if the desired verification flow is supported.

AR# 12576
Date Created 08/29/2007
Last Updated 03/03/2014
Status Archive
Type General Article