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AR# 12630

5.1i CORE Generator - Known issues for XilinxCoreLib compilation regarding VSS and VCS

Description

Keywords: CORE Generator, COREGen, XilinxCoreLib, behavioral, models, simulator, VSS, VCSi, VHDL, Verilog, compile, locally, static, elaboration

Urgency: Standard

General Description:
When I compile XilinxCoreLib with Synopsys VSS or VCSi HDL compilers, errors are reported for the following files:

VSS
convolution_v1_0.vhd
lfsr_v1_0.vhd
mult_gen_v3_0.vhd
mult_gen_v2_0.vhd

VCSi
v32fft_v2_0.v (CR141750)
C_ADDSUB_V2_0.v
C_DA_1D_DCT_V1_0.v
mult_gen_v3_1.v
MAC_V1_1.v
MAC_V1_0.v
ENCODE_8B10B_V1_0.v
DECODE_8B10B_V1_0.v
C_DDS_V2_0.v
C_BIT_CORRELATOR_V2_0.v

-----------------------------------------------------------------------------------------------------------------------
vhdlan -i -nc -w XilinxCoreLib /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/lfsr_v1_0.vhd
'1' WHEN c_size-1,
^
**Error: vhdlan,1027 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/lfsr_v1_0.vhd(191):
Case alternative choice must be locally static.
-----------------------------------------------------------------------------------------------------------------------
vhdlan -i -nc -w XilinxCoreLib /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/convolution_v1_0.vhd
"0123456789";VARIABLE II111OIOII1IIOOOlO1I011OI0I0lIIIII:STRING(1 TO 11);BEGIN IF IOIlII1I0O0l1l1O110O0IOlO0O1lIIIII<0 THEN IF IOIlII1I0O0l1l1O110O0IOlO0O1lIIIII=-2147483648 THEN RETURN("-2147483648");ELSE
^
**Error: vhdlan,973 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/convolution_v1_0.vhd(34):
Integer overflow while scanning numeric literal.
-----------------------------------------------------------------------------------------------------------------------
vhdlan -i -nc -w XilinxCoreLib /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v3_0.vhd
constant out_size : integer := find_ccm_out_width(b_input, c_baat+c_b_width, c_baat) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v3_0.vhd(521):
Cannot read signal during static elaboration.
signal full_out_size : integer := find_ccm_out_width(b_input, c_a_width+c_b_width, c_a_width) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v3_0.vhd(523):
Cannot read signal during static elaboration.
constant b_is_0 : boolean := b_input'length = 1 and b_input(0)='0' and c_mult_type = 2;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v3_0.vhd(527):
Cannot read signal during static elaboration.
-----------------------------------------------------------------------------------------------------------------------
vhdlan -i -nc -w XilinxCoreLib /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd
signal b_input : std_logic_vector((find_ccm_b_width(str_to_slv(c_b_value, c_b_width), c_b_width, c_mult_type, c_has_loadb)-1) downto 0) := set_b_value(b); ^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(505):
Cannot read signal during static elaboration.
signal bconst0 : std_logic_vector((find_ccm_b_width(str_to_slv(c_b_value, c_b_width), c_b_width, c_mult_type, c_has_loadb)-1) downto 0) := set_b_value(b); ^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(506):
Cannot read signal during static elaboration.
signal bconst1 : std_logic_vector((find_ccm_b_width(str_to_slv(c_b_value, c_b_width), c_b_width, c_mult_type, c_has_loadb)-1) downto 0) := set_b_value(b); ^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(507):
Cannot read signal during static elaboration.
signal out_size : integer := find_ccm_out_width(b_input, c_baat+c_b_width, c_baat) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(508):
Cannot read signal during static elaboration.
signal full_out_size : integer := find_ccm_out_width(b_input, c_a_width+c_b_width, c_a_width) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(509):
Cannot read signal during static elaboration.
constant b_is_0 : boolean := b_input'length = 1 and b_input(0)='0' and c_mult_type = 2;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(513):
Cannot read signal during static elaboration.
signal din_b_seq : std_logic_vector((find_ccm_b_width(str_to_slv(c_b_value, c_b_width), c_b_width, c_mult_type, c_has_loadb)-1) downto 0) := set_b_value(b); ^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(567):
Cannot read signal during static elaboration.
signal padding : integer := (c_baat * (no_of_cycles-1)) - c_a_width ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(580):
Cannot read signal during static elaboration.
signal cycle : integer := no_of_cycles+1 ; --1;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(581):
Cannot read signal during static elaboration.
signal rfd_f_pipe: std_logic_vector((1 + c_reg_a_b_inputs - ccm_serial) downto 0) := (others => '1');
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(594):
Cannot read signal during static elaboration.
std_logic_vector (out_size-no_sign downto 0) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(596):
Cannot read signal during static elaboration.
std_logic_vector (out_size-no_sign downto 0) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(596):
Cannot read signal during static elaboration.
signal intRFD_delay: std_logic_vector((no_of_cycles-c_reg_a_b_inputs-1) downto 0) := (others => '0');
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(600):
Cannot read signal during static elaboration.
variable product : std_logic_vector((out_size-no_sign) downto 0) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(963):
Cannot read signal during static elaboration.
variable product : std_logic_vector((out_size-no_sign) downto 0) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(963):
Cannot read signal during static elaboration.
variable feedback : std_logic_vector((out_size-no_sign) downto 0);
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(964):
Cannot read signal during static elaboration.
variable feedback : std_logic_vector((out_size-no_sign) downto 0);
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(964):
Cannot read signal during static elaboration.
variable all0s : std_logic_vector((out_size-no_sign) downto 0) := (others => '0') ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(965):
Cannot read signal during static elaboration.
variable all0s : std_logic_vector((out_size-no_sign) downto 0) := (others => '0') ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(965):
Cannot read signal during static elaboration.
variable store : std_logic_vector(((c_baat*(no_of_cycles-2))-1) downto 0) := (others => '0');
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(966):
Cannot read signal during static elaboration.
variable accum_out : std_logic_vector(out_size downto 0) := (others => '0') ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(967):
Cannot read signal during static elaboration.
variable total_output : std_logic_vector((out_size + 1 + (c_baat*(no_of_cycles-2)) - 1) downto 0) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(968):
Cannot read signal during static elaboration.
variable total_output : std_logic_vector((out_size + 1 + (c_baat*(no_of_cycles-2)) - 1) downto 0) ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(968):
Cannot read signal during static elaboration.
variable diff : integer := (out_size + 1 + (c_baat*(no_of_cycles-2))) - (((no_of_cycles-1)*c_baat) - c_a_width) - c_out_width ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(969):
Cannot read signal during static elaboration.
variable diff : integer := (out_size + 1 + (c_baat*(no_of_cycles-2))) - (((no_of_cycles-1)*c_baat) - c_a_width) - c_out_width ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(969):
Cannot read signal during static elaboration.
variable diff : integer := (out_size + 1 + (c_baat*(no_of_cycles-2))) - (((no_of_cycles-1)*c_baat) - c_a_width) - c_out_width ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(969):
Cannot read signal during static elaboration.
variable intNDpipe : std_logic_vector(mult_length downto 0) := (others => '0') ;
^
**Error: vhdlan,826 /products/xirsqa/merged/E_IP1.14/vhdl/src/XilinxCoreLib/mult_gen_v2_0.vhd(974):
Cannot read signal during static elaboration.

-----------------------------------------------------------------------------------------------------------------------
Warning-[SIOB] Select index out of bounds
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_ADDSUB_V2_0.v
", 168: C_B_VALUE[((C_B_WIDTH * 8) - 1):((C_B_WIDTH - 1) * 8)]
Warning-[SIOB] Select index out of bounds
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_ADDSUB_V2_0.v
", 168: C_B_VALUE[((C_B_WIDTH * 8) - 1):((C_B_WIDTH - 1) * 8)]
Warning-[SIOB] Select index out of bounds
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_ADDSUB_V2_0.v
", 168: C_B_VALUE[((C_B_WIDTH * 8) - 1):((C_B_WIDTH - 1) * 8)]
Warning-[SIOB] Select index out of bounds
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_ADDSUB_V2_0.v
", 168: C_B_VALUE[((C_B_WIDTH * 8) - 1):((C_B_WIDTH - 1) * 8)]
-----------------------------------------------------------------------------------------------------------------------
Error-[MTL] Memory too large
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/VFFT32_V2_0.v
", 11413: shifter
-----------------------------------------------------------------------------------------------------------------------
Warning-[ZONMCM] Zero or negative multiconcat multiplier
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_DA_1D_DCT_V1_0.v
", 309: {(full_precision_width - result_width) {1'b0}}
this will be replaced by 1'b0
1 unique modules to generate
Error: Vector half too large (/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_DA_1D_DCT_V1_0.v line 279)
Error: Vector fractional_part too large (/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_DA_1D_DCT_V1_0.v line 279)

-----------------------------------------------------------------------------------------------------------------------
Parsing design file '/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/mult_gen_v3_1.v'
Error-[SFCOR] Source file cannot be opened for reading
Source file "XilinxCoreLib/C_REG_FD_V3_0.v" cannot be opened for
reading.
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/mult_gen_v3_1.v
", 17: token is '`include "XilinxCoreLib/C_REG_FD_V3_0.v"
'
`include "XilinxCoreLib/C_REG_FD_V3_0.v"
----------------------------------------------------------------------------------------------------------------------
Warning-[SIOB] Select index out of bounds
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_1.v",
698: a_int[1]
Warning-[SIOB] Select index out of bounds
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_1.v",
699: a_int[1]
Error-[IRIPS] Illegal range in part select
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_1.v",
911: acc_out_int[(C_ACC_WIDTH - 1):(C_ACC_WIDTH - C_OUT_WIDTH)]
Error-[IRIPS] Illegal range in part select
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_1.v",
999: acc_out_int[(C_ACC_WIDTH - 1):(C_ACC_WIDTH - C_OUT_WIDTH)]
Error-[IRIPS] Illegal range in part select
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_1.v",
1145: p[(C_P_WIDTH - 1):(C_P_WIDTH - C_OUT_WIDTH)]
------------------------------------------------------------------------------------------------------------------------
Error-[IRIPS] Illegal range in part select
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_0.v",
912: acc_out_int[(C_ACC_WIDTH - 1):(C_ACC_WIDTH - C_OUT_WIDTH)]
Error-[IRIPS] Illegal range in part select
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_0.v",
1000: acc_out_int[(C_ACC_WIDTH - 1):(C_ACC_WIDTH - C_OUT_WIDTH)]
Error-[IRIPS] Illegal range in part select
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_0.v",
1146: p[(C_P_WIDTH - 1):(C_P_WIDTH - C_OUT_WIDTH)]
Warning-[SIOB] Select index out of bounds
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_0.v",
1262: control[2]
Warning-[SIOB] Select index out of bounds
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/MAC_V1_0.v",
1265: control_del[2]
-----------------------------------------------------------------------------------------------------------------------
Parsing design file '/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/ENCODE_8B10B_V1_0.v'
1 Unresolved modules/udps:
encode_8b10b_v1_base
Design has unresolved objects. Must exit.
Errors: 1
-----------------------------------------------------------------------------------------------------------------------
Parsing design file '/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/DECODE_8B10B_V1_0.v'
1 Unresolved modules/udps:
decode_8b10b_v1_base
Design has unresolved objects. Must exit.
Errors: 1
-----------------------------------------------------------------------------------------------------------------------
Parsing design file '/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_DDS_V2_0.v'
Error-[SE] Syntax error
"/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_DDS_V2_0.v
", 156 (expanding macro): token is '('
`library("PHASE_ACCUMULATOR","ovi_xilinxcorelib")
^
1 error
-----------------------------------------------------------------------------------------------------------------------
Parsing design file '/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_BIT_CORRELATOR_V2_0.v'
Top Level Modules:
C_BIT_CORRELATOR_V2_0
No TimeScale specified
Error-[IRIPS] Illegal range in part select
"
/products/xirsqa/merged/E_IP1.14/verilog/src/XilinxCoreLib/C_BIT_CORRELATOR_V2_0.v
", 173: psc_din[(C_DATA_WIDTH - 1):1]
1 error
-----------------------------------------------------------------------------------------------------------------------

Solution

The errors listed above have not been detected by MTI simulators; therefore, if you have access to one, using an MTI simulator is a way to work around this problem.

Most of the above warning messages can be ignored; however, the cores with error messages will not be compiled and cannot be used to perform simulation.

For the above cores that have errors, you must skip behavioral simulation and run post-NGDBuild simulation, which is described in (Xilinx Answer 8065).
AR# 12630
Date Created 08/29/2007
Last Updated 03/04/2008
Status Archive
Type General Article