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AR# 12682

Schematic - DRC flags an error when a design element uses a VHDL keyword, even if the design flow is set to Verilog; "" is a reserved keyword for VHDL

Description

Although I am using a Verilog synthesis flow, the following error messages occur when I synthesize schematics:

"WARNING:Portability:111 - Message file "SchematicEditor.msg" wasn't found.

ERROR:Schematic Editor - "in" is a reserved keyword for vhdl.

ERROR:Schematic Editor - "out" is a reserved keyword for vhdl.

EXEWRAP detected a return code of '1' from program 'sch2verilog'"

Similar errors occur when I use Verilog keywords in a VHDL project flow.

Solution

ECS 5.1i

ECS 5.1i does not support the use of either VHDL or Verilog keywords as net or component names. To work around this problem, change the name of the signal so that it is not a keyword in either language (e.g., INPUT, OUTPUT, IN, OUT, INOUT are not acceptable).

ISE 6.1i and later

The keyword check is controlled by user preferences as follows for each HDL flow:

The Verilog flow runs the Sch2Verilog program, and the VHDL flow runs the Sch2VHDL program. These two programs run schematic Design Rule Checking (DRC). In the schematic editor, select Edit -> Preferences, and highlight the Schematic Editor Check options. If the "Check VHDL Reserved Keywords" preference is not set, Sch2Verilog does not check for VHDL keywords (Sch2VHDL does). If the "Check VHDL Reserved Keywords" preference is set, both Sch2Verilog and Sch2VHDL check for VHDL keywords.

If the "Check Verilog Reserved Keywords" preference is not set, Sch2VHDL does not check for Verilog keywords (Sch2Verilog does). If the "Check Verilog Reserved Keywords" preference is set, then both Sch2Verilog and Sch2VHDL check for Verilog keywords.

AR# 12682
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article