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AR# 12728

4.1i ECS - SCH2Verilog causes memory leak when complex busses are used


Keywords: SCH2Verilog, schematic

Urgency: Standard

General Description:
The use of complex busses in ECS causes a memory leak for SCH2Verilog.


The only way to work around this problem is to create buffers that isolate the ports from the combination of the bus.

This problem is fixed in the latest 4.1i Service Pack, available at:
The first service pack containing the fix is 4.1i Service Pack 3.
AR# 12728
Date Created 10/02/2001
Last Updated 08/11/2003
Status Archive
Type General Article