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AR# 12757

4.1i CORE Generator - When the "Add Pads" option is used, clock buffers are not correctly inserted in a Virtex-II

Description

Keywords: CORE Generator, COREGen, add, pads, IBUFG, BUFG, global, dedicated, clock, CLK, I/O, IO, skew, delay, Virtex, Virtex-II

Urgency: Standard

General Description:
An option in 4.1i CORE Generator allows the insertion of I/O pads to the ports of the core. In the main COREGen GUI, under Project Options -> Output Products, in the Elaboration Options section, there is an "Add Pad" option. When this option is selected, IPAD or OPAD are inserted for general I/O ports of the core. This can be seen in the generated .edif netlist.

For the clock ports, a BUFG is properly being inserted for XC4000 or Spartan Families. For Virtex and Spartan-II cores, an IBUFG is inserted, which is acceptable.

In Virtex-II devices, COREGen also inserts an IBUFG. However, in Virtex-II, the IBUFG needs to be followed by an BUFG; the BUFG is not being inserted, so the clock port is not really using the global clock resources.

As a result, when MAP is run, the following warning may appear:

"WARNING:MapLib:277 - Dedicated Clock IO IBUFG symbol "BU312" (output signal=N2) is not driving a global clock buffer or a DLL. This configuration will result in high clock skew and long net delay."

This is the case for 4.1i IP Update #1 (E_IP1). (In 4.1i (without E_IP1), the IBUFG was not even inserted for Virtex and Virtex-II. Instead, a BUFG was inserted, which caused problems for Virtex as well as Virtex-II. For more information on this, please see (Xilinx Answer 12018)).

With E_IP1, the IBUFG is now being inserted properly for Virtex, but the problem still remains for Virtex-II.

Solution

This problem will be fixed in 4.1i IP Update #2, which is scheduled for release at the end of February, 2002.

Meanwhile, if you need to have the clock ports using the global clock resources, we recommend that you generate the core without the "Add Pads" option. For HDL flow, use the generated wrapper file, which will have the appropriate instantiation of the core along with the IPAD and OPAD.

Then, manually instantiate IBUFG and BUFG for the clock signals. If you are using a schematic flow, generate the core without the "Add Pads" option, and instantiate the core in the schematic along with the appropriate IPAD, OPAD, IBUFG, and BUFG.
AR# 12757
Date Created 10/04/2001
Last Updated 10/09/2003
Status Archive
Type General Article