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AR# 12773

3.6.x FPGA Express - "ERROR:Place:1747 - The IOB ddr_ad[8] is locked to site L13 in Bank 3. This violates the Select I/O banking rules."

Description

Keywords: FPGA, 4.1, SP1, IOSTANDARD, SSTL, Express, Synopsys, IBUF, OBUF, Select I/O

Urgency: Standard

General Description:
When instantiating Select I/O buffers, FPGA Express may change the buffer from the standard instantiated to LVTTL. This has occurred with at least the SSTL2 standard. This change generates the following Place and Route error:

"ERROR:Place:1747 - The IOB ddr_ad<8> is locked to site L13 in Bank 3. This violates the Select I/O banking rules."

Solution

If you wish to instantiate various Select I/O buffers, the recommended method from the Libraries Guide (Xilinx Manual "Libraries Guide", page 344) is to instantiate the IBUF/OBUF, then to place the appropriate I/O standard on the component. For examples, please refer to (Xilinx Answer 10900).

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 2.

Please downoad and install the FPGA Express version that is available with Service Pack 2.
AR# 12773
Date Created 10/05/2001
Last Updated 08/11/2003
Status Archive
Type General Article