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AR# 12802

6.1i PrimeTime - What is formal verification?


Keywords: PrimeTime, formal, verification, 4.1i, 5.1i

Urgency: Standard

General Description:
What is formal verification?



Formal verification is an algorithmic-based approach to logic verification that exhaustively proves a design's functional properties. Typically, there are two types of formal verification:

1. Equivalence Checking - This verifies the functional equivalence of two designs, which can be at the same or different abstraction levels (e.g., RTL-to-RTL, RTL-to-Gate, or Gate-to-Gate). It is used for design implementation verification.

2. Model Checking - This verifies that the implementation satisfies the properties of the design. It is used early in the design creation phase to detect functional bugs.

PrimeTime is a Static Timing Analyzer tool, and Formality is a Formal Verification Tool.


For related PrimeTime information, please also see the following Answer Records:

(Xilinx Answer 12803) - "What types of users will be interested in the formal verification flow?"
(Xilinx Answer 12804) - "Does Xilinx support equivalence checking and model checking?"
(Xilinx Answer 12805) - "Does Xilinx support equivalency checking for RTL-to-RTL, RTL-to-Gate, or Gate-to-Gate?"
(Xilinx Answer 12806) - "Why does Xilinx support equivalency checking?"
(Xilinx Answer 12807) - "Does Xilinx plan to support model checking?"
(Xilinx Answer 12808) - "Should equivalency checking replace simulation?"
(Xilinx Answer 12809) - "When should I use equivalency checking?"
(Xilinx Answer 12810) - "How will I benefit from using equivalency checking?"
(Xilinx Answer 12811) - "Can I use equivalency checking to re-target an FPGA to an ASIC? If so, how?"
(Xilinx Answer 12812) - "Which equivalency-checking tool vendors does Xilinx support?"
(Xilinx Answer 12813) - "What platforms does Xilinx support?"
(Xilinx Answer 12814) - "I am a current Formality/Conformal customer. Who should I contact for support-related issues?"
(Xilinx Answer 12815) - "Are application notes regarding verification flow available?"
(Xilinx Answer 12816) - "What are the limitations of the verification flows?"
(Xilinx Answer 12817) - "Does the verification flow work with the Synopsys FCII, Synplicity Synplify, and Mentor LeonardoSpectrum synthesis tools?"
(Xilinx Answer 12818) - "Does the verification flow work with all languages?"
(Xilinx Answer 12820) - "Who supplies libraries?"
(Xilinx Answer 12821) - "What libraries does Xilinx provide?"
(Xilinx Answer 12822) - "How do I install the libraries that are referenced by Xilinx Application Note 411?"
(Xilinx Answer 12823) - "What Xilinx product families are supported?"
AR# 12802
Date Created 10/09/2001
Last Updated 06/23/2004
Status Archive
Type General Article