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# AR# 12819

## Description

The timing tools are adding or subtracting half of the period to OFFSET constraints for DDR flip-flops and negative-edge-clocked output flip-flops (FFs).

How do I constrain these?

## Solution

Solution 1 (to be used only if DDR is clocked by local inversion):

Constraining DDR with local inversion (i.e., using the positive and negative edges of the same clock) properly requires that two sets of constraints be created.

The first is a group and constraint for the positive edge FFs, and the second is a group and adjusted constraint for the falling edge FFs.

The steps are as follows:

1. Create a PERIOD constraint on the original clock, grouping the DDR flip-flops.
2. Create a group of the I/O pads.
3. Create a sub-group of the falling edge flip-flops.
4. Create an OFFSET constraint for the DDR group.
5. Create an adjusted OFFSET constraint for the falling edge flip-flops (*).

(*) The adjustment is needed to take into account the difference between clock edges.
Assuming that the PERIOD constraint specifies a HIGH starting edge, for the negative flip-flops group, subtract half of the clock period from the OFFSET IN requirement and add half of the clock period to the OFFSET OUT requirement.

For example:

# Input clock has a period of 16 ns.
# OFFSET requirement is 10 ns before on inputs and 12 ns after on outputs.

# Step 1. Create a PERIOD constraint on the original clock, grouping the DDR flip-flops.

NET "main_clk" TNM_NET = "main_clk_grp";
TIMESPEC "TS_main_clk" = PERIOD "main_clk_grp" 16 ns HIGH 50%;

# Step 2. Group the I/O pads.

INST DDR_inputs* TNM = IN_DDR; # IN_DDR includes only pads
INST DDR_outputs* TNM = OUT_DDR; # OUT_DDR includes only pads

# Step 3. Create a sub-group of the falling edge flip-flops.

TIMEGRP "falling_reg" = FALLING "main_clk_grp"; # Falling _reg includes synchronous elements

# OR

INST "IN_DDR_01" TNM = "falling_reg"; # Falling_reg includes synchronous elements

# Step 4. Create an OFFSET constraint for the DDR group.

TIMEGRP "IN_DDR" OFFSET = IN 10 ns BEFORE "main_clk";
TIMEGRP "OUT_DDR" OFFSET = OUT 12 ns AFTER "main_clk";

# Step 5. Create an adjusted OFFSET constraint for the falling edge flip-flops.

TIMEGRP "IN_DDR" OFFSET = IN 2 ns BEFORE "main_clk" TIMEGRP "falling_reg"; # User Manually Adjusts the Requirement
TIMEGRP "OUT_DDR" OFFSET = OUT 20 ns AFTER "main_clk" TIMEGRP "falling_reg"; # User Manually Adjusts the Requirement

For duty cycles other than 50-50 that are specified with a HIGH PERIOD TIMESPEC, take the difference from the rising edge to the falling edge and apply it to the negative edge group.
For a PERIOD constraint that is specified with a Low starting edge, apply the falling-edge-to-rising-edge time to the positive edge group.

This Answer Record still applies to non-DDR negative edge registers in all software versions after 4.1i.

For more details on timing constraints, please see the Timing Constraints User Guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf

Solution 2 (to be used only if DDR is clocked by CLK0 and CLK180 of the DCM/PLL/MMCM):

Constraining DDR clocked by CLK0 and CLK180 of a DCM properly also requires that two sets of constraints be created.
The first is a group and constraint for flip-flops clocked by CLK0, and the second is a group and adjusted constraint for the flip-flops clocked by CLK180.

The steps are as follows:
1. Create a PERIOD constraint on the original clock, grouping the DDR flip-flops.
2. Create a group of the I/O pads.
3. Create sub-groups of flip-flops clocked by CLK0 and CLK180.
4. Create an OFFSET constraint for the DDR group.
5. Create an adjusted OFFSET constraint for the flip-flops clocked by CLK180 group (*).

(*) The adjustment needs be done to take into account the shifted clock edge of CLK180.

Assuming that the PERIOD constraint specifies a HIGH starting edge, for the flip-flops clocked by CLK180, subtract half of the clock period from the OFFSET IN requirement and add half of the clock period to the OFFSET OUT requirement.

For example:

# Input clock has a period of 16 ns.
# OFFSET requirement is 10 ns before on inputs and 12 ns after on outputs.
# CLK0 and CLK180 are the name of clock signals output by DCM CLK0 and CLK180 ports.
# Step 1. Create a PERIOD constraint on the original clock, grouping the DDR flip-flops.

NET "main_clk" TNM_NET = "main_clk_grp";
TIMESPEC "TS_main_clk" = PERIOD "main_clk_grp" 16 ns HIGH 50%;

# Step 2. Group the I/O pads.

INST DDR_inputs* TNM = IN_DDR; # IN_DDR includes only pads
INST DDR_outputs* TNM = OUT_DDR; # OUT_DDR includes only pads

# Step 3. Create sub-groups of flip-flops clocked by CLK0 and CLK180.

NET "CLK0" TNM_NET = "clk0_grp"; # Group FFs that are clocked by DCM CLK0 output
NET "CLK180" TNM_NET = "clk180_grp"; # Group FFs that are clocked by DCM CLK180 output

# Step 4. Create an OFFSET constraint for the DDR group.

TIMEGRP "IN_DDR" OFFSET = IN 10 ns BEFORE "main_clk" TIMEGRP "clk0_grp";
TIMEGRP "OUT_DDR" OFFSET = OUT 12 ns AFTER "main_clk" TIMEGRP "clk0_grp";

# Step 5. Create an adjusted OFFSET constraint for the flip-flops clocked by CLK180 group (*).

TIMEGRP "IN_DDR" OFFSET = IN 2 ns BEFORE "main_clk" TIMEGRP "clk180_grp"; # User Manually Adjusts the Requirement
TIMEGRP "OUT_DDR" OFFSET = OUT 20 ns AFTER "main_clk" TIMEGRP "clk180_grp"; # User Manually Adjusts the Requirement

This Answer Record still applies to non-DDR registers clocked by CLK180 in all software versions after 4.1i.

For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug612.pdf

Solution 3 (to be used only if DDR is clocked by CLK0 of the DCM/PLL/MMCM):

The steps are as follows:

1. Create a PERIOD constraint on the original clock, grouping the DDR flip-flops.
2. Create a group of the I/O pads.
3. Create an OFFSET constraint for the DDR group using RISING and FALLING keywords.

For example:

# Input clock has a period of 16 ns.
# OFFSET requirement is 10 ns before on inputs and 12 ns after on outputs.
# Step 1. Create a PERIOD constraint on the original clock, grouping the DDR flip-flops.

NET "main_clk" TNM_NET = "main_clk_grp";
TIMESPEC "TS_main_clk" = PERIOD "main_clk_grp" 16 ns HIGH 50%;

# Step 2. Group the I/O pads.

INST DDR_inputs* TNM = IN_DDR; # IN_DDR includes only pads
INST DDR_outputs* TNM = OUT_DDR; # OUT_DDR includes only pads

# Step 3. Create an OFFSET constraint for the DDR group.

TIMEGRP "IN_DDR" OFFSET = IN 10 ns BEFORE "main_clk" RISING";
TIMEGRP "OUT_DDR" OFFSET = OUT 12 ns AFTER "main_clk" RISING;
TIMEGRP "IN_DDR" OFFSET = IN10 ns BEFORE "main_clk" FALING;
TIMEGRP "OUT_DDR" OFFSET = OUT12 ns AFTER "main_clk"FALLING;

For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug612.pdf

AR# 12819
Date 11/25/2014
Status Active
Type General Article
Tools
• ISE Design Suite
• ISE
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